APPLICATION SPECIFIC INTEGRATED CIRCUITS

RTL Design and Verification

Category Description: The RTL (Register-Transfer Level) design phase is where your chip's functionality is defined. We provide end-to-end services, from initial architecture to RTL coding and functional verification, ensuring your design meets performance and functionality requirements.

Design and verification

Platforms

Processors- ARM, X86, Tensilica, Microblaze, Picoblaze
Boards- Altera, xilinx based multi-FPGA boards
Emulators – Zebu, Veloce & Palladium

Interfaces

AXI, AHB, APB, PLB
PCIE, SATA, DDR
MAC, USB
SDIO
MIPI – DSI, MIPI- CSI
WLAN 802.11 a/b/p/g
H264 Decoders
CAN , I2C, SPI, UART
DMA, CRYPTO, PRNG

Tools

Synthesis Tools – Xilinx Vivado, Xilinx ISE, Altera Quartus, Mentor Precision, Cadence Quiclturn
Partition Tools – Synopsis Certify
Simulation- Modelsim, Questasim, Cadence NCSim & Quickturn
System Debug – ARM realview ICE, Xilinx chipscope, Altera signaltap, Synopsis Identify, Debussy, J-Link, Trace-32

RTL Details

Architecture Exploration and Definition

RTL Coding (VHDL, Verilog)

Functional Verification (Simulation, Emulation)

Code Coverage Analysis and Bug Fixing

Synthesis Constraints Preparation

Synthesis and Optimization

Category Description: Once your RTL design is complete, we transform it into gate-level representations for further optimization. Our synthesis and optimization services focus on achieving the best possible performance, power, and area characteristics.

Synthesis and Optimization Details

RTL-to-Gate Synthesis

Technology Mapping

Timing Constraints Setup

Power Optimization

Area Reduction Techniques

Design for Test (DFT)

we understand that ensuring the manufacturability and reliability of your integrated circuits is crucial. Our comprehensive Design for Test (DFT) services are tailored to optimize the testability and ease of manufacturing for your ASICs and custom designs.

Design for Test (DFT) Details

Scan Chain Insertion

ATPG (Automatic Test Pattern Generation)

Test Logic Insertion: Integrating test logic, such as BIST (Built-In Self-Test) controllers.

Memory BIST

Boundary Scan (JTAG)

Fault Models

DFT Simulation

Test Coverage Analysis

DFT Signoff

Physical Design and Placement

Category Description: The physical design phase determines the chip's layout and placement of logic cells, optimizing for area, power, and performance. We employ state-of-the-art tools and methodologies for precise physical design.

Physical Design and Placement Details

Floorplanning and Area Budgeting

Placement and Legalization

Clock Tree Synthesis (CTS)

Signal Routing and Optimization

Power Distribution Network (PDN) Design

Static Timing Analysis (STA)

Category Description: STA is a critical step in ensuring that your ASIC meets its timing requirements. Our STA services include comprehensive analysis to guarantee that your chip performs as intended, addressing setup and hold times, clock domains, and more.

Static Timing Analysis (STA) Details

Setup and Hold Time Analysis

Clock Domain Crossing (CDC) Checks

Critical Path Identification and Optimization

Minimizing Clock Skew

Multi-Mode and Multi-Voltage (MMV) STA

Timing Closure and Signoff

Category Description: Ensuring that your ASIC meets timing requirements is paramount. Our team focuses on closing timing paths and performing rigorous signoff checks to guarantee that your chip performs as intended.

Timing Closure and Signoff Details

Static Timing Analysis (STA)

Setup and Hold Time Fixing

Clock Domain Crossing (CDC) Analysis

DRC (Design Rule Check) and LVS (Layout vs. Schematic) Verification

EDA Tool-Specific Signoff Checks

GDSII Tapeout and Manufacturing Support

Category Description: The final stage involves preparing the GDSII data for chip fabrication. We assist in tapeout, working closely with foundries and providing the necessary support to ensure a smooth transition to manufacturing.

GDSII Takeout and Manufacturing Support Details

GDSII Data Preparation and Review

DFM (Design for Manufacturability) Checks

Foundry Interface and Coordination

Post-Tapeout Support

Yield Enhancement Strategies

Contact Us

Location

# 25,2nd Floor, Beside St. Theresa School, B Narayanapura, Mahadevapura, Bengaluru, Karnataka 560016

Support

info@siyacon.com

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